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advance data sheet march 1997 L8575 dual-resistive, low-cost subscriber line interface circuit (slic) features n two channels in a single package n serial data interface n per-channel powerdown n low standby power ( 65 mw per channel) n integrated protection n no external protection device required n battery noise cancellation n switchhook detector n ring-trip detector n switchhook and ring-trip detector self-test n fault detector n zero ring voltage cross detection n three relay drivers per channel n 44-pin, surface-mount, plastic package (plcc) description the L8575 is a dual-resistive, low-cost subscriber line interface circuit (slic) that is optimized to meet both itu-t recommendations and lssgr require- ments for 600 w /900 w resistive and complex imped- ance termination applications. it interfaces the low- voltage circuits on an analog line card to the tip and ring of two subscriber loops. the L8575 does not supply dc current to the subscriber loops?xternal resistors are used for this purpose. the device is built using a 90 v complementary bipolar (cbic) process and is available in a 44-pin plcc package.
L8575 advance data sheet dual-resistive, low-cost slic march 1997 2 lucent technologies inc. table of contents contents page features .................................................................................................................................................................. 1 description ...............................................................................................................................................................1 preliminary pin information ..................................................................................................................................... 5 absolute maximum ratings (@ t a = 25 c) ............................................................................................................ 8 electrical characteristics ......................................................................................................................................... 9 relay drivers ..................................................................................................................................................... 11 transmission...................................................................................................................................................... 13 serial interface and logic .................................................................................................................................. 14 applications ........................................................................................................................................................... 16 general .............................................................................................................................................................. 16 resistor module................................................................................................................................................. 16 protection .......................................................................................................................................................... 18 tip/ring drivers ................................................................................................................................................. 20 receive interface............................................................................................................................................... 20 transmit interface .............................................................................................................................................. 20 battery noise cancellation ................................................................................................................................ 20 on-hook transmission....................................................................................................................................... 21 self-test............................................................................................................................................................. 21 serial data interface .......................................................................................................................................... 21 operating states.................................................................................................................................................... 24 active state........................................................................................................................................................ 24 test state........................................................................................................................................................... 24 powerdown state with relay driver rdd operated .......................................................................................... 24 powerdown state............................................................................................................................................... 24 ringing state (d2 = 1) ....................................................................................................................................... 24 supervision............................................................................................................................................................ 25 off-hook detection ............................................................................................................................................ 25 ring-trip threshold ........................................................................................................................................... 25 ring-trip requirements......................................................................................................................................25 fault detection................................................................................................................................................... 26 zero voltage current cross ............................................................................................................................... 26 relay drivers ..................................................................................................................................................... 26 dc characteristics .................................................................................................................................................. 27 i/v characteristics ............................................................................................................................................. 27 loop length....................................................................................................................................................... 27 ac design............................................................................................................................................................... 28 codec features and selection summary.......................................................................................................... 28 design equations .............................................................................................................................................. 29 application diagram ..............................................................................................................................................33 outline diagram..................................................................................................................................................... 35 44-pin plcc...................................................................................................................................................... 35 ordering information ..............................................................................................................................................36
lucent technologies inc. 3 advance data sheet L8575 march 1997 dual-resistive, low-cost slic table of contents (continued) tables page table 1. pin descriptions .......................................................................................................................................... 5 table 2. operating conditions and powering ............................................................................................................9 table 3. battery feed, switchhook detectors (lca and lcb), and fault detectors (flta and fltb)................... 10 table 4. ring-trip detectors (rta, rtb, rza, and rzb) ....................................................................................... 10 table 5. relay drivers (rdra, rdta, rdrb, rdtb, rdda, and rddb)............................................................. 11 table 6. analog signal pins .................................................................................................................................... 11 table 7. transmission characteristics..................................................................................................................... 13 table 8. logic inputs (clk, en, and di) and outputs (do).................................................................................... 14 table 9. timing requirements for clk, en, di, and do ........................................................................................ 14 table 10. mmc * a31a8575aa thick film resistor module.................................................................................... 17 table 11. total module power dissipation .............................................................................................................. 19 table 12. truth table for en and clk ..................................................................................................................... 22 table 13. output data bit de?ition .......................................................................................................................22 table 14. input data bit de?ition.......................................................................................................................... 23 table 15. truth table for d1 and d0........................................................................................................................ 24 table 16. external components required ...............................................................................................................33 figures page figure 1. functional diagram ....................................................................................................................................4 figure 2. 44-pin plcc pinout .................................................................................................................................. 5 figure 3. power supply rejection vs. frequency diagram ..................................................................................... 15 figure 4. L8575 slic resistor module................................................................................................................... 17 figure 5. L8575 slic dual-resistive matching requirements .............................................................................. 18 figure 6. self-test mode circuit ............................................................................................................................. 21 figure 7. timing requirements for clk, en, di, and do ...................................................................................... 22 figure 8. logic diagram (positive logic; flip-flops clocked on high-to-low transition) ....................................... 23 figure 9. ring-trip threshold ................................................................................................................................. 25 figure 10. ring-trip circuits ...................................................................................................................................25 figure 11. L8575 slic i/v template .......................................................................................................................27 figure 12. equivalent complex terminations ..........................................................................................................29 figure 13. initial ac interface for complex termination between L8575 slic and t7504 codec ..........................30 figure 14. revised ac interface c t and c r combined into a single capacitor c s ..................................................31 figure 15. addition of resistor r sc from xmt to irp .............................................................................................32 figure 16. typical application diagram with blocking capacitors (c b ) included ....................................................34 * mmc is a registered trademark of microelectronic modules corporation.
L8575 advance data sheet dual-resistive, low-cost slic march 1997 4 lucent technologies inc. description (continued) 12-3304(f).ar1 figure 1. functional diagram relay driver relay driver serial data interface, latches, and logic relay driver relay driver axa ring-trip detector a receive interface and battery noise cancellation a + control detectors v bat switchhook and fault detectors a v bat tip current source a ring current source a axb + v bat switchhook and fault detectors b ring-trip detector b receive interface and battery noise cancellation b v bat tip current source b ring current source b rdda rdra dgnd v ddd di do clk en rdtb rdrb tsa rsa pta rtpa rtna pra tsb rsb ptb rtpb rtnb prb rgbnb cbnb irpb vrnb xmtb cfltb rgbna cbna irpa vrna v dda agnd v bat xmta cflta nrtb v bat tstb pdb v bat tsta pda nrta nlca nflta relay driver rdra +5d relay driver rddb +5 a v bat npltb nlcb
lucent technologies inc. 5 advance data sheet L8575 march 1997 dual-resistive, low-cost slic preliminary pin information 12-3364(f) figure 2. 44-pin plcc pinout table 1. pin descriptions pin symbol type name/function 1 nc no connect. unused pin (no internal connection). 2 do o serial data output. data in the internal 8-bit serial shift register is shifted out on this logic output with the clock signal on pin clk. 3 di i serial data input. data on this logic input is shifted into the 8-bit serial shift register with the clock signal on pin clk. 4 cfltb i/o fault filter (channel b). connect a 0.1 m f capacitor from cfltb to agnd. this capaci- tor ?ters tip/ring transients from the channel b fault detector. 5 v ddd 5 v digital dc supply. 5 v supply for logic and relay driver ?back diodes. 6 dgnd digital ground. ground for channel b relay drivers. 7 rddb o disconnect relay driver (channel b). this output drives the external relay. 8 rdrb o ringing relay driver (channel b). this output drives an external ringing relay. 9 rdtb o test relay driver (channel b). this output drives an external test relay. 10 rtpb i ring-trip positive (channel b). positive sense input for the ring-trip detector. rdra rtpa rdta xmta tsa rsa rgbna vrna rtpb rdtb rdrb xmtb tsb rsb rgbnb vrnb 7 9 10 11 12 13 14 15 16 17 8 6 4 3 2 1 4443424140 5 18 20 21 22 23 24 25 26 27 28 19 39 37 36 35 34 33 32 31 30 29 38 rddb rtnb rtna pta pra agnd cbna cbnb agnd ptb prb v ddd di nc cfltb clk do en dgnd cflta v ddd dgnd rdda irpa v bat v dda v bat irpb L8575
L8575 advance data sheet dual-resistive, low-cost slic march 1997 6 lucent technologies inc. preliminary pin information (continued) table 1. pin descriptions (continued) pin symbol type name/function 11 rtnb i ring-trip negative (channel b). negative sense input for the ring-trip detector. 12 xmtb o transmit signal output (channel b). channel b transmit ampli?r output. 13 tsb i tip sense (channel b). negative input of channel b transmit op amp. connect one high- value resistor between tsb and the tip of loop b and another high-value resistor between tsb and xmtb. 14 rsb i ring sense (channel b). positive input of channel b transmit op amp. connect one high- value resistor between rsb and the ring of loop b and another high-value resistor between rsb and agnd. 15 rgbnb i battery noise gain resistor (channel b). the current ?wing out of prb is 50 times the current ?wing into rgbnb. connect a resistor from rgbnb to agnd to set the gain of the channel b battery noise cancellation circuit. 16 vrnb i receive voltage negative input (channel b). the differential current ?wing from ptb to prb is ?00 times the voltage applied to vrnb, divided by the impedance connected between irpb and agnd. 17 irpb i receive current positive input (channel b). the differential current ?wing from ptb to prb is 200 times the current ?wing into irpb. 18 ptb o protected tip (channel b). output of the tip current drive ampli?r b. connect ptb to the tip of loop b through an overvoltage protection resistor (1.4 k w minimum). 19 prb o protected ring (channel b). output of the ring current drive ampli?r b. connect prb to the ring of loop b through an overvoltage protection resistor (1.4 k w minimum). 20 agnd analog signal ground. signal ground for channel b. 21 v bat of?e battery supply. negative of?e battery supply for channel b. 22 cbnb i battery noise capacitor (channel b). the current ?wing out of prb is ?0 times the voltage applied to cbnb, divided by the impedance connected between rgbnb and agnd. couple v bat to cbnb through a high-pass ?ter to eliminate battery noise from the tip/ring of channel b. 23 v dda 5 v analog dc supply. 24 cbna i battery noise capacitor (channel a). the current ?wing out of pra is ?0 times the voltage applied to cbna, divided by the impedance connected between rgbna and agnd. couple v bat to cbna through a high-pass ?ter to eliminate battery noise from the tip/ring of channel a. 25 v bat of?e battery supply. negative of?e battery supply for channel a. 26 agnd analog signal ground. signal ground for channel a. 27 pra o protected ring (channel a). output of the ring current drive ampli?r a. connect pra to the ring of loop a through an overvoltage protection resistor (1.4 k w minimum). 28 pta o protected tip (channel a). output of the tip current drive ampli?r a. connect pta to the tip of loop a through an overvoltage protection resistor (1.4 k w minimum). 29 irpa i receive current positive input (channel a). the differential current ?wing from pta to pra is 200 times the current ?wing into irpa. 30 vrna i receive voltage negative input (channel a). the differential current ?wing from pta to pra is ?00 times the voltage applied to vrna, divided by the impedance connected between irpa and agnd.
lucent technologies inc. 7 advance data sheet L8575 march 1997 dual-resistive, low-cost slic preliminary pin information (continued) table 1. pin descriptions (continued) pin symbol type name/function 31 rgbna i battery noise gain resistor (channel a). the current ?wing out of pra is 50 times the current ?wing into rgbna. connect a resistor from rgbna to agnd to set the gain of the channel a battery noise cancellation circuit. 32 rsa i ring sense (channel a). positive input of channel a transmit op amp. connect one high-value resistor between rsa and the ring of loop a and another high-value resis- tor between rsa and agnd. 33 tsa i tip sense (channel a). negative input of channel a transmit op amp. connect one high-value resistor between tsa and the tip of loop a and another high-value resistor between tsa and xmta. 34 xmta o transmit signal output (channel a). channel a transmit ampli?r output. 35 rtna i ring-trip negative (channel a). negative sense input for the ring-trip detector. 36 rtpa i ring-trip positive (channel a). positive sense input for the ring-trip detector. 37 rdta o test relay driver (channel a). this output drives an external test relay. 38 rdra o ringing relay driver (channel a). this output drives the external ringing relay. 39 rdda o disconnect relay driver (channel a). this output drives an external relay. 40 dgnd digital ground. ground for channel a relay drivers. 41 v ddd 5 v digital dc supply. 5 v supply for logic and relay driver ?back diodes. 42 cflta i/o fault filter (channel a). connect a 0.1 m f capacitor from cflta to agnd. this capacitor ?ters tip/ring transients from the channel a fault detector. 43 en i enable. a high-to-low transition on this logic input latches the data in the 8-bit serial shift register into the output latches. the logic level of en also controls which data is shifted into the 8-bit serial shift register (refer to clk pin description). 44 clk i clock. when the enable input (en) is high, a low-to-high transition on this logic input shifts data at the data input pin (di) into the 8-bit serial shift register. when the enable input (en) is low, a low-to-high transition latches the states of the internal detectors into the 8-bit serial shift register.
L8575 advance data sheet dual-resistive, low-cost slic march 1997 8 lucent technologies inc. absolute maximum ratings (@ t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. notes: analog and battery voltages are referenced to agnd; digital (logic) voltages are referenced to dgnd. the ic can be damaged unless all ground connections are applied before, and removed after, all other connections. furthermore, when power- ing the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. some of the known examples of conditions that cause such potentials during powering are (1) an inductor connected to tip and ring that can force an overvoltage on v bat through external components if the v bat connection chatters, and (2) inductance in the v bat lead that could reso- nate with the v bat ?ter capacitor to cause a destructive overvoltage. parameter symbol min value max unit 5 v analog dc supply v dda ?.5 +7.0 v 5 v digital dc supply v ddd ?.5 +7.0 v office battery supply v bat ?5 +0.5 v logic input voltage ?.5 v ddd + 0.5 v logic input clamp diode current, per pin 20 ma logic output voltage ?.5 v ddd + 0.5 v logic output current, per pin (excluding relay drivers) 35 ma maximum junction temperature 150 c operating temperature range ?0 +125 c storage temperature range t stg ?0 +125 c relative humidity range 5 95 % ground potential difference (dgnd to agnd) +0.5 ?.5 v
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 9 electrical characteristics generally, minimum and maximum values are testing requirements. however, some parameters may not be tested in production because they are guaranteed by design and device characterization. typical values re?ct the design center or nominal value of the parameter; they are for information only and are not a requirement. minimum and maximum values apply across the entire temperature range (?0 c to +85 c) and entire battery range (?2 v to ?8 v). unless otherwise speci?d, typical values are de?ed as 25 c, v dda = 5 v, v ddd = 5 v, v bat = ?8 v. posi- tive currents ?w into the device. table 2. operating conditions and powering 1. not to exceed 26 grams of water per kilogram of dry air. 2. includes v bat current through the external dc feed resistors, assuming the loop is open. 3. includes power dissipation in the external dc feed resistors per application diagram, assuming the loop is open. 4. v bat power supply rejection depends on the battery noise cancellation circuit. the performance stated here applies only during the active state and assumes proper battery noise cancellation, i.e., a high-pass ?ter from v bat to cbn and a resistor from rgbn to agnd which is 50 times the dc feed resistor connecting v bat to ring (refer to the application diagram). 5. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter min typ max unit temperature range ?0 85 c humidity range 5 95 1 %rh supply voltage: v dda v ddd v bat v dda ?v ddd 4.75 4.75 ?2 ?8 5.5 5.5 ?8 0.5 v v v v supply currents (both channels active): i vdda + i vddd (5 v) i vbat (?8 v) 2 19.0 ?7.5 ma ma supply currents (both channels powerdown): i vdda + i vddd (5 v) i vbat (?8 v) 2 18.0 ?.0 ma ma total power dissipation (5 v; ?8 v) 3 : active (both channels) powerdown (both channels) 1.40 185 w mw power-supply rejection 4, 5 (50 mvrms ripple): tip/ring and xmt refer to figure 3. thermal 5 : thermal resistance (still air) operating tjc 47 155 c/w c
L8575 advance data sheet dual-resistive, low-cost slic march 1997 10 lucent technologies inc. electrical characteristics (continued) table 3. battery feed, switchhook detectors (lca and lcb), and fault detectors (flta and fltb) 1. assumes 2 x 300 w external dc feed resistors. 2. detector values are independent of of?e battery and are valid over the entire range of v bat . 3. fault voltage is de?ed as the absolute value of the dc voltage across either dc feed resistor. if the voltage across either feed resistor exceeds this value, a fault is determined to be present. flt is forced to a 0 when d2 = 1 (ringing state). table 4. ring-trip detectors (rta, rtb, rza, and rzb) 1. the ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. 2. rt must also indicate ring-trip when the ac ringing voltage is absent (<5 vrms) from the ringing source. 3. pretrip: ringing must not be tripped by a 10 k w resistor in parallel with an 8 m f capacitor applied across tip and ring. parameter min typ max unit loop resistance range 1 : (3.17 dbm overload into 600 w ) i loop = 18 ma at v bat = ?8 v 1800 w longitudinal current capability per wire 8.5 marms switchhook detector loop resistance 2 : off-hook (lc = 1) on-hook (lc = 0) 4800 4000 3200 w w w fault detector 2, 3 : | v tip | or | v ring ?v bat | no fault (flt = 0) fault (flt = 1) detection delay t det (no fault to fault; cflt = 0.1 m f) release delay (fault to no fault; cflt = 0.1 m f) 39 10 1.6 t det 36 36 33 30 2.5 t det v v ms ms parameter min typ max unit ringing source 1 : frequency ( | ) dc voltage ac voltage 19 ?9.5 60 20 28 ?7 105 hz v vrms ring trip 2, 3 (rt = 1): loop resistance trip time ( | = 20 hz) rt valid 2000 200 80 w ms ms ringing source zero crossing (referenced to v bat /2): ringing voltage positive (rz = 1) ringing voltage negative (rz = 0) 3v bat /4 v bat /4 v v
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 11 electrical characteristics (continued) relay drivers the relay drivers operate using the v ddd supply. when v ddd is ?st applied to the device, the relay drivers must power up and remain in the off-state until the slic is con?ured via the serial data interface. the table below sum- marizes their parameter requirements. table 5. relay drivers (rdra, rdta, rdrb, rdtb, rdda, and rddb) 1. unless otherwise speci?d, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. table 6. analog signal pins 1.this parameter is not tested in production. it is guaranteed by design and device characterization. parameter 1 symbol min max unit off-state output current (v out = v ddd )i off 10 m a on-state output voltage (i out = 40 ma) v on 0 0.60 v on-state output voltage (i out = 20 ma) v on 0 0.40 v clamp diode reverse current (v out = 0) i r 10 m a clamp diode on voltage (i out = 80 ma) v oc v ddd + 0.5 v ddd + 3.0 v turn-on time 2 t on 10 m s turn-off time 2 t off 10 m s parameter min typ max unit pta, ptb, pra, and prb: surge current (from external source): continuous 1 ms exponential pulse (50 repetitions) 1 second, 60 hz (60 repetitions) 10 m s rectangular pulse (10 repetitions) 50 750 175 1.25 madc ma marms a output drive (pta and ptb): drive current (sink only) voltage swing (i out = 15 ma) dc bias current (active state only) 0.1 v bat + 4 5.3 5.6 15 agnd 5.9 ma v ma output drive (pra and prb): drive current (source only) voltage swing (i out = 15 ma) dc bias current (active state only) ?5 v bat ?.3 ?.6 ?.1 agnd ?4 ?.9 ma v ma output impedance (60 hz?.4 khz) 1 output load resistance (dc or ac) 1 1 0 100 m w k w
L8575 advance data sheet dual-resistive, low-cost slic march 1997 12 lucent technologies inc. electrical characteristics (continued) relay drivers (continued) table 6. analog signal pins (continued) 1.this parameter is not tested in production. it is guaranteed by design and device characterization. 2.a v bat or ground short on xmta or xmtb will not cause a device failure. parameter min typ max unit xmta and xmtb: output drive current output voltage swing (3 ma load): maximum minimum 3 v bat v bat + 10 v dda +2.5 ma v v output short-circuit current 2 output impedance (60 hz?.4 khz) output load dc resistance output load ac impedance 1 output load capacitance 1 20 2 30 10 50 ma w k w k w pf vrna and vrnb: input voltage range input bias current input impedance 1 ?.75 20 3.5 1 v m a m w irpa and irpb: input offset voltage (to respective vrn) input impedance 10 5 mv w cbna and cbnb: input voltage range input bias current input impedance ?.75 50 3.5 250 v na m w rgbna and rgbnb: input offset voltage (to respective cbn) input impedance 10 5 mv w tsa, tsb, rsa, and rsb: surge current (from external source) input voltage range input bias current differential input impedance 1 common-mode input impedance 1 external capacitance (67 k w source impedance) 1 v bat + 3 50 50 25 agnd 1 10 madc v m a k w m w pf
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 13 electrical characteristics (continued) transmission transmit direction is tip/ring to xmt. receive direction is irp/vrn to tip/ring. table 7. transmission characteristics 1. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. 2. assumes ideal external components. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. transmission characteristics are speci?d assuming a 600 w resistive termination; however, feedback using external components allows the user to adjust the termination impedance from the intrinsic 600 w of the feed resistors to most itu-t recommended complex termination impedances. 5. measured with the L8575 slic connected per application diagram with ideal external components. parameter min typ max unit longitudinal balance ( ieee 1 std. 455?976) 2 : 50 hz? khz 1 khz? khz 54 50 70 66 db db metallic to longitudinal balance 2 : 200 hz? khz 30 db rfi rejection 3 : (0.5 vrms, 50 w source, 30% am mod. 1 khz) 500 khz?0 mhz 10 mhz?00 mhz ?5 ?5 dbv dbv tip/ring signal level 3.17 dbm ac termination impedance 4 600 w total harmonic distortion (200 hz? khz) 3 0.3 % transmit gain ( | = 1 khz) 5 : tip/ring to xmt ?.486 ?.500 ?.514 receive gain ( | = 1 khz): irp current to differential current flowing from pt to pr vrv to irp 195 0.995 200 1 205 1.005 cbn gain ( | = 1 khz): 1 rgbn current to current flowing cbn to rgbn ?9.5 0.995 ?0 1 ?0.5 1.005 gain vs. frequency (transmit & receive; 1 khz reference) 3 : 200 hz?.4 khz ?.1 0 0.1 db gain vs. level (transmit & receive; 0 dbv reference) 3 : ?0 db to +3 db ?.05 0 0.05 db interchannel crosstalk 3 : 200 hz?.4 khz 77 db idle-channel noise (tip/ring; 600 w termination): psophometric 3 c-message 3 khz ?t 3 ?7 12 20 dbmp dbrnc dbrn idle-channel noise (xmt; 600 w termination): psophometric 3 c-message 3 khz ?t 3 ?7 12 20 dbmp0 dbrnc0 dbrn0
L8575 advance data sheet dual-resistive, low-cost slic march 1997 14 lucent technologies inc. electrical characteristics (continued) serial interface and logic the tables below summarize the parameter and timing requirements for logic inputs clk, en, di, and do. table 8. logic inputs (clk, en, and di) and outputs (do) 1. unless otherwise speci?d, all logic voltages are referenced to dgnd. 2.this parameter is not tested in production. it is guaranteed by design and device characterization. table 9. timing requirements for clk, en, di, and do 1.unless otherwise speci?d, all times are measured from the 50% point of logic transitions. 2.this parameter is not tested in production. it is guaranteed by design and device characterization. parameter 1 symbol min max unit high-level input voltage v ih 2v ddd v low-level input voltage v il 0 0.8 v input bias current (high and low) i in 50 m a high-level output voltage (i out = ?00 m a) v oh v ddd ?1.5 v ddd v low-level output voltage (i out = 180 m a) v ol 0 0.4 v output short-circuit current (v out = v ddd ) i oss 1 35 ma output load capacitance 2 c ol 0 50 pf parameter 1 symbol min max unit input rise and fall time, clk & en (10% to 90%) 2 t r , t f 070ns maximum input capacitance 2 c in ?pf maximum clk frequency (50% duty cycle) f max 1.25 mhz propagation delay, clk to do 2 t pco 0 350 ns propagation delay, en to rd outputs 2 t pcr 010 m s minimum setup time from di to clk 2 t sdc 150 ns minimum setup time from di to en 2 t sde 150 ns minimum setup time from en to clk 2 t sec 150 ns minimum hold time from clk to di 2 t hdc 50 ns minimum hold time from en to clk 2 t hec 50 ns minimum pulse width of clk t wck 400 ns minimum pulse width of en t wen 800 ns
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 15 electrical characteristics (continued) serial interface and logic (continued) 12-3307(f) figure 3. power supply rejection vs. frequency diagram 10 1 ?0 ?0 ?0 ?0 0 frequency (hz) psrr (db) ?0 ?0 10 2 10 3 10 4 10 5 10 6 v dda (metallic) v bat (metallic)
L8575 advance data sheet dual-resistive, low-cost slic march 1997 16 lucent technologies inc. applications general the L8575 is a dual (channels a and b) subscriber line interface circuit (slic). each channel operates inde- pendently such that no interaction occurs between the channels. the following description applies to both channels though the description may refer to only a sin- gle channel. some circuits, such as reference circuits which do not impact interchannel crosstalk, are com- mon to both channels. the L8575 device supplies a precise differential current to the tip/ring pair (via pt and pr) as a function of analog signal voltages on irp and vrn. however, the current drivers connected to pt and pr are not designed to supply dc feed current to the loop. two external resistors (typically 300 w ), connected to of?e battery and ground, must be used in conjunction with the L8575 slic to provide dc loop current. these resis- tors will primarily determine the longitudinal balance of the line feed; thus, they must be matched appropriately to meet the longitudinal balance requirements (0.4% for 50 db balance). these resistors also have a signi?ant impact on the termination impedance of the slic. feedback, using external components, allows the user to adjust the ter- mination impedance from the intrinsic 600 w of the feed resistors to most itu-t recommended complex termi- nation impedances. since the L8575 does not supply dc to the loop, outputs pt and pr can be coupled to the tip and ring through a resistance high enough to allow for simple lightning protection of the drivers. how- ever, the resistance must be low enough to achieve the coupling of suf?ient ac signals to the tip and ring from the available power supply. since the tip and ring drivers are current sources, the value of the resistance is arbitrary and does not affect the performance of the slic. a minimum value of 1400 w (1.4 k w ) is required for protection purposes. the L8575 also senses the tip voltage, ring voltage, and differential tip/ring voltage via the ts and rs sense inputs. the differential dc voltage is used inter- nally for switchhook detection. the tip and ring volt- ages are also used internally to detect faults on tip and ring. both detector thresholds are preset internally. the status of each detector is monitored at pin do by reading the 8-bit serial shift register. the differential tip/ring ac signal appears on analog output xmt. the L8575 also includes: n per-channel ring-trip detectors, loop closure detec- tors. n six relay drivers (three per channel). n 8-bit serial-to-parallel and parallel-to-serial logic interface. n per-channel circuits which eliminate the battery noise that is coupled to the tip and ring through the dc feed resistors. n fault detection. n zero ring voltage detection. resistor module the L8575 requires certain external resistors at the tip and ring interface. because of matching and protec- tion requirements, one of the most economical options recommended to implement these registers is in a thick ?m resistor module. a schematic and a brief descrip- tion of the function of each of these resistors is given in figure 4. note that microelectronic modules corpora- tion* mmc a31a8575aa thick film resistor module is an application-speci? resistor module designed for use with the L8575 slic. the values, tolerance, match- ing, and power rating of the mmc a31a8575aa mod- ule are given in table 10. resistors r 1 and r 2 are the dc feed resistors. r 1 is connected from battery to ring, and r 2 is connected from tip to ground. the dc loop current is fed to the subscriber loop via these resistors. these resistors will set the dc i/v template of the line circuit with the i/v template being linear with a ?/600 w slope. no con- stant current region at short dc loops is provided by resistors r 1 and r 2 , or the L8575 slic. * for additional information, contact microelectronic modules corporation ( mmc ), 2601 s. moorland rd., new berlin, wi 53151: u.s.a: (414) 785-6506 fax number: (414) 785-6516
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 17 applications (continued) resistor module (continued) 5-3428(f) note: pin numbers are mmc a31a8575aa pin numbers. resistors are labeled per mmc a31a8575aa description. nodes are L8575 slic package nodes. figure 4. L8575 slic resistor module table 10. mmc a31a8575aa thick film resistor module note: for 50 db longitudinal balance, 0.2% for 58 db balances. continuous power (rms). resistor value tolerance power surge rating r 1 300 w 1.0% 2.0 w lightning: power cross r 2 300 w 1.0% 2.0 w lightning: power cross r 3 100 k w 1.0% 250 mw none r 4 100 k w 1.0% 250 mw none r 5 200 k w 1.0% 250 mw lightning: power cross r 6 200 k w 1.0% 250 mw lightning: power cross r 7 1.4 k w 2.0% 0.5 w lightning: power cross r 8 1.4 k w 2.0% 0.5 w lightning: power cross r 9 15 k w 10 mw none r 9 /r 1 50 1.0% r 1 /r 2 1 0.35% (r 3 + r 6 )/(r 4 + r 5 ) 1 0.35% tip 15 fuse tip 19 17 r 7 6pr ring r 1 v bat r 9 rgbn gnd r 3 rs 10 9 8 7 5 fuse ring 1 3 r 4 ts xmt 12 11 r 5 r 2 r 8 r 6 gnd 13 pt 14 resistors r 1 and r 2 also provide a common-mode impedance of (300 || 300) 150 w . these resistors will primarily determine the longitudinal balance of the line circuit; thus they must be matched appropriately to meet longitudinal balance requirements (0.35% for 50 db and 0.2% for 58 db). also, they have a signi? cant impact on the termination impedance of the slic. feedback using external components (external compo- nents when a ?st- or second-generation codec is used) allows the user to set the termination impedance at 600 w, or most itu-t recommended complex termi- nation impedances. resistors r 1 and r 2 , along with r 3 and r 7 , are used in conjunction with the self-test feature of the L8575 slic. in this mode, the ring current drive ampli?r is saturated to ground, and the tip ampli?r is saturated to battery, which causes both the ring-trip and loop clo- sure detectors to trip. ring-trip and loop closure detec- tor output are bits rt and lc, respectively, in the serial output stream. under normal operating conditions, resistors r 1 and r 2 will see the battery voltage less the tip/ring voltage. assuming a tip/ring voltage of 6 v (representative of a short into a handset), the nominal continuous operating power of r 1 and r 2 is given by: (48 v ?6 v) 2 /600 w = 2.94 w per r 1 and r 2 resistor pair 2.94 w/2 = 1.47 w per resistor the operating power rating of r 1 and r 2 is 2 w. this is the steady-state power rating of r 1 and r 2 , and it is adequate for normal operating conditions. the ability of these resistors to withstand fault conditions depends on the power ratings of the individual resistors and on the power rating of the thick ?m resistor module itself. obviously, the higher the power capabilities of the resistor module, the less susceptible the resistors are to damage during faults. the various fault conditions are discussed further in the protection section of this data sheet.
L8575 advance data sheet dual-resistive, low-cost slic march 1997 18 lucent technologies inc. applications (continued) resistor module (continued) resistors r 3 through r 6 set the gain of the slic in the transmit (2-wire to 4-wire) direction. this is shown in figure 5. 5-3422(f) figure 5. L8575 slic dual-resistive matching requirements the matching of resistors r 3 through r 6 will determine the gain accuracy of the slic; therefore, these resis- tors must also be matched accordingly. the matching requirements are given in table 10. because of the high resistance values, the normal operating power of resistors r 3 through r 6 will be rela- tively low. given design margin and thick ?m technol- ogy capabilities, a power rating of 250 mw for these resistors is not unreasonable. resistors r 7 and r 8 are used to couple the pt and pr current drive ampli?rs to tip and ring. since the pt and pr drive ampli?rs are current sources, the value of the series resistance does not affect the loop length or other performance of the slic, and may be arbi- trarily high for protection purposes. a value of 1.4 k w is adequate for protection purposes. under normal operating conditions, these resistors will see the battery voltage less the tip/ring voltage. assuming a tip/ring voltage of 6 v (representative of a short into a handset), the nominal continuous operating power of r 7 and r 8 is given by: (48 v ?6 v) 2 /2.8 k w = 0.630 w per r 7 and r 8 resistor pair 630 mw/2 = 315 mw per resistor (r 7 and r 8 ) hence, the operating power rating of 500 mw for r 7 and r 8 . this is the nominal rating for r 7 and r 8 under normal operating conditions. again, the ability of these resistors to withstand fault conditions depends on the power rating. resistor r 9 is also included on the thick ?m resistor module. this resistor is used to set the gain of the bat- tery noise cancellation circuit. see the battery noise cancellation section of this data sheet for design equa- tions to set the value of r 9 . protection because of the resistive feed architecture, a simple inexpensive protection scheme that does not require a separate external protection device may be used. the mmc a31a8575aa resistor module has speci?ations which are quali?d to bellcore gr-core-1089, ul *1459, ul 497a, fcc part 68.302 (d) & (e) and rea form 397g, itu-t k20, and itu-t k21. lightning and power cross protection are provided by the two dc feed resistors, r 1 and r 2 , in the external resistor module. under fault conditions, these resistors serve as fault current-limiting resistors. fault current is steered to ground and to battery via resistors r 2 and r 1 , respectively. thus, the battery design must be such that the various speci?d faults can be applied to the battery through 300 w, without damaging the battery or the line circuit. resistors r 1 and r 2 need to be designed to survive lightning surges and to dissipate power associated with a ring ground dc fault and speci?d ac power cross faults?oth a sneak under and full surge type fault. under certain sustained fault conditions, r 1 and r 2 could fail when they are required to survive. for this reason, a per-channel fault detector is included on the L8575 slic. when the voltage across either r 1 and/or r 2 is greater than a nominal 36 v, the fault detect bit (flt) in the serial data output will go high. the control logic on the line card detects flt is high, and opens an external electromechanical relay (emr) to isolate the resistors from the loop, enabling the resistors to service extended power cross. (note the emr is the test in or test out emr, and this relay is driven by one of the internal relay drivers on the L8575 slic.) a delay of 10 ms to 30 ms is provided (using an exter- nal capacitor on pin cflt) in the fault detector. this prevents transients on the tip and ring from tripping the fault detector when a fault is not present. * ul is a registered trademark of underwriters laboratories, inc. + tip ring r 5 200 k w r 6 200 k w r 3 100 k w xmt r 4 100 k w
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 19 applications (continued) protection (continued) the tip/ring drive ampli?rs, which feed the ac signal to nodes pr and pt, are high-impedance current driv- ers. since these nodes are current sources, the value of protection current-limiting series resistance does not affect the loop length or other slic performance, and may be arbitrarily high for protection purposes. resistors r 7 and r 8 in the resistor module are used for this purpose. these resistors have a value of 1.4 k w with a power rating 0.5 w. internal diodes clamp nodes pr and pt to ground and battery. the voltage sense leads, rs and ts, are also exposed to the outside plant. current to these nodes is limited by resistors r 3 and r 4 in the resistor module. resistors r 3 and r 4 are 100 k w , 250 mw resistors. internal diodes also clamp nodes rs and ts to ground and battery. the ability of the resistors to survive faults is a function of the power dissipated in the individual resistors and the total power dissipated on the entire thick ?m mod- ule. fault conditions include: n a continuous worst-case (fault detector) sneak under condition of 39 vdc applied metallically to ring in the case of a ring ground fault, and n a sneak under condition of 39 vp (voltage peak) applied to tip and ring, as described in bellcore 1089, itu-t k20, etc., in the case of power cross. additionally, there is a transient fault condition, assum- ing full speci?d power cross fault voltages (bellcore 1089, itu-t k20, etc.,) for a time duration equal to the maximum response time that it will take to isolate the line circuit from the fault via the fault detector and emr described above. for example, a ring ground fault assuming fault detec- tor sneak under will result in a worst-case potential across the r 1 of 39 v. the power dissipated in r 1 under this condition is calculated as follows: (39 v * 39 v)/300 w = 5 w since this is a sneak under condition, the fault detector will not trigger and the time duration of the fault can be in?ite. in the case of a longitudinally applied sneak under power cross, the maximum voltage seen, this time by both r 1 (ring) and r 2 (tip), is 39 vp (voltage peak). the power dissipation is given by: maximum voltage = 39 vp = 27.6 vrms maximum power = (27.6 vrms * 27.6 vrms)/(300 w ) = 2.54 w per resistor. thus, 2.54 w will be dissipated per resistor or a total of 5.1 w in a longitudinal sneak under condition. if r 1 and r 2 are rated for 2 w, they can fail under these fault conditions. also, the mmc a31a8575aa resistor module includes a fail-safe thermal fuse located at the tip and ring nodes (pin 1 and pin 19) of the module for this reason. a fail-safe fuse is recommended for any resistor module used with the L8575 slic. with thick ?m technology, not only is the power capa- bilities of the individual resistors important, but also the power handling capabilities of the entire module. the total module power dissipation is calculated by sum- ming the power dissipation for each of the resistors under a given condition. for example, the module power dissipation for the above sneak under fault conditions is calculated in table 11. thus, the hic will require a minimum power rating of 6 w continuous to survive these sneak under conditions. table 11. total module power dissipation resistor (r) value ( w ) ring ground maximum dc fault voltage (v) ring ground maximum dc fault power (w) longitudinal fault maximum peak voltage (vp) longitudinal fault maximum rms voltage (vrms) longitudinal fault maximum rms power (w) 1 300 39 5.07 39 27.577 2.535 2 300 0 0 39 27.577 2.535 3 100 k 29 0.015 39 27.577 0.0076 4 100 k 0 0 39 27.577 0.0076 5 200 k 39 0.0076 39 27.577 0.0038 6 200 k 0 0 39 27.577 0.0038 7 1.4 k 39 1.086 39 27.577 0.543 8 1.4 k 0 0 39 27.577 0.543 total hic power: 6.18 6.18
L8575 advance data sheet dual-resistive, low-cost slic march 1997 20 lucent technologies inc. applications (continued) protection (continued) similar consideration to the individual resistor and total module power capability should be given to full voltage power faults, but taking into account the fault detector will isolate the slic and resistor module after some ?ite period of time. the fault detector indicates a fault in the serial data output stream in 10 ns to 30 ms. rec- ognition and relay activation time need to be consid- ered. tip/ring drivers each channel of the L8575 utilizes a current source for the tip/ring driver. the driver is capable of sinking (but not sourcing) up to 15 ma from the tip (pt) while swinging to within 4 v of of?e battery (v bat ), and sourcing (but not sinking) up to 15 ma to the ring (pr) while swinging to within 4 v of ground (agnd). since the current driver is not bidirectional, during transmis- sion (powerup) each lead is biased at 5.6 madc. receive interface the receive interface circuitry couples the differential signal on receive inputs irp and vrn to the tip/ring drivers. input irp is a low-impedance (<5 w ) current input while vrn is a high-impedance voltage input. internal feedback forces the voltage at irp to be equal to vrn such that a voltage applied to vrn causes a current ?w out of irp, which equals that voltage divided by the impedance connected from irp to agnd (assuming the input voltage is referenced to agnd). the receive interface and tip/ring drivers provide a current gain of 200, i.e., a differential output current ?ws from pt to pr which is 200 times the current ?wing into irp. the receive interface also provides a level shift since the inputs, irp and vrn, are refer- enced to analog ground, while the outputs, pt and pr, swing between agnd and v bat . the receive interface ensures that the input current is not converted to a common-mode current at pt and pr. transmit interface the transmit interface circuitry interfaces the differen- tial voltage on tip and ring to transmit output xmt. the tip/ring differential voltage (both ac and dc) appears on output xmt with a gain of 0.5. the transmit interface uses an operational ampli?r with four external resistors to perform a differential to single-ended conversion. output xmt is referenced to ground (agnd). the longitudinal balance and gain accuracy at xmt depends on the matching of the external resistors. because a large dc potential exists at xmt, a capacitor must be used to couple the ac signal to the low-voltage codec circuitry. the operational ampli?r inputs are ts and rs. these inputs are also used by the fault-detec- tion circuitry to detect fault voltages on tip or ring. a fault is detected when the magnitude of the voltage across either dc feed resistor exceeds a nominal 36 v (equivalent to approximately 4 w dissipation in either resistor). a delay is provided (using an external capaci- tor on pin cflt) in the fault detector. this prevents transients on tip and ring from tripping the fault detec- tor when a fault is not actually present. battery noise cancellation the battery noise cancellation circuit senses the ac noise on the battery via the capacitor connected from input cbn to v bat . it then couples this noise, 180 degrees out of phase, to the ring current driver ampli?r. this cancels the battery noise that is coupled to the ring through the feed resistor connected to v bat . additionally, it ensures longitudinal balance which depends only on the matching of the battery feed resis- tors by creating an ac ground at v bat with respect to signals on the ring lead. for the cancellation to operate properly, both the phase and gain must be accurate. the battery noise cancella- tion gain is a transconductance that is equal to 50 divided by resistor r9 on the thick ?m resistor module connected from rgbn to ground (agnd). this value must be equal to the reciprocal of the dc feed resistor (1/300 w ), that is, it is advantageous if the two resistors are matched and tracked thermally, i.e., located on the same ?m inte- grated circuit (fic). 50 r 9 ------ - 1 300 w ---------------- = r 9 15 k w =
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 21 applications (continued) on-hook transmission in powerup mode, the L8575 slic provides a dc bias of 5.6 ma. the 5.6 ma bias is also present under on- hook conditions. the L8575 slic is able to support on- hook transmission because of this bias. it is suf?iently high to drive a 3.17 dbm signal into a 600 w or 900 w loop under open-circuit conditions. an internal current source provides a dc bias of 112 m a. there is an inter- nal current gain of 50; thus (50 * 112 m a) 5.6 ma ?ws from battery through r 1 to pr, and 5.6 ma ?ws from pt through r 2 to ground under on-hook conditions. self-test the L8575 slic offers a self-test capability. this is set via logic inputs d1 and d0 in the serial input data stream. in this mode, shown in figure 6, the ring cur- rent drive ampli?r is saturated to ground, and the tip ampli?r is saturated to battery, which causes both the ring-trip and loop closure detectors to indicate an off- hook condition. in this operation mode, the ring relay must not be active. the ring relay driver output in the L8575 is at package nodes rdr (a&b). these relay drivers are controlled by logic inputs d2 (a&b) in the serial input data stream. see table 14 for details. 12-3423(f).r2 figure 6. self-test mode circuit serial data interface a 4-wire serial interface (di, do, clk, and en) is used to pass data from the control logic on the line card to the L8575 slic, and to pass detector information from L8575 slic to the control logic on the line card. when enable input en is high, data on input di is clocked into an 8-bit shift register on a high-to-low transition of the clock input clk. eight latches (four per channel) are provided to store the data. data is loaded into the eight latches from input di and the ?st 7 bits of the shift register on the high-to-low transition of en. when en is low, a high-to- low transition on clk loads all of the detector informa- tion (loop closure, fault zero voltage, and ring-trip from the internal detector circuitry) into the 8-bit shift regis- ter. when en is high, data in the 8-bit shift register is clocked out on output do on the high-to-low transition of clk. two latch outputs per channel drive relay drivers. the drivers are included on the L8575 slic. these are the relay drivers whose outputs are at external package nodes rdr (a&b) and rdt (a&b). the remaining two latch output power channels are internal control sig- nals. these are logic data bits d0 (a&b) and d1 (a&b). these bits input to a combinational logic circuit that controls the operational state of each channel and also controls the state of the third relay driver. the third relay drivers output is at external package node rdd (a&b). refer to the truth table (see table 15) for more details. note that up to 16 channels may be daisy-chained together. the do lead of package 1 (channels 1 and 2) may be tied to the di lead of package 2 (channels 3 and 4), etc. all en and clk should also be tied together in this mode. the L8575 slic device has an internal reset which guarantees that all relay drivers power up in the off- state when 5 v (v ccd and v cca ) is applied to the device. this reset operates properly only if input en is held high (within 0.5 v of v ccd ) when the 5 v is applied. an external pull-up resistor from the en bus to v ccd satis?s this requirement, provided that the logic- driving en does not pull the en bus low during pow- erup. + lca/b + rta/b pr ptp rtn 200 k w 200 k w 1.4 k w r 1.0 m w 0.1 m f 1.0 m w 8.25 m w 300 w v ring v bat 100 k w pt t 1.4 k w 100 k w 300 k w
L8575 advance data sheet dual-resistive, low-cost slic march 1997 22 lucent technologies inc. applications (continued) serial data interface (continued) figure 7 shows the timing characteristics and requirement de?itions. 12-3305(f).ar2 figure 7. timing requirements for clk, en, di, and do table 12. truth table for en and clk table 13. output data bit de?ition en clk function 1 shift register clocked, qn = qn ?1; latches unaffected. 0 channel data latched into shift register; latches unaffected. x contents of shift register transferred to output latches. data bit output output bit definition d0a d0a latch output state d0a (refer to operating states section). d1a d1a latch output state d1a (refer to operating states section). d2a rdra ringing relay driver a is on (rdra low = relay energized) when d2a = 1. d3a rdta test relay driver a is on (rdta low = relay energized) when d3a = 1. d0b d0b latch output state d0b (refer to operating states section). d1b d1b latch output state d1b (refer to operating states section). d2b rdrb ringing relay driver b is on (rdrb low = relay energized) when d2b = 1. d3b rdtb test relay driver b is on (rdtb low = relay energized) when d3b = 1. di en clk do t sde t wen t hdc t sdc t hec t sec t wck t wck t pco
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 23 electrical characteristics (continued) serial data interface (continued) table 14. input data bit de?ition 12-3306(f).br3 figure 8. logic diagram (positive logic; flip-flops clocked on high-to-low transition) input data bit input bit de?ition rza d0a channel a ringing voltage zero crossing detector output (positive = 1). flta d1a channel a fault detector output (loop fault = 1). rta d2a channel a ring-trip detector output (ring-trip = 1). lca d3a channel a switchhook detector output (off-hook = 1). rzb d0b channel b ringing voltage zero crossing detector output (positive = 1). fltb d1b channel b fault detector output (loop fault = 1). rtb d2b channel b ring-trip detector output (ring-trip = 1). lcb d3b channel b switchhook detector output (off-hook = 1). rza d0 d1 sel q d q q d0a d0a di clk en flta d0 d1 sel q d q q d1a d1a rta d0 d1 sel q d q q d2a rdra lca d0 d1 sel q d q q d3a rdta rzb d0 d1 sel q d q q d0b d0b fltb d0 d1 sel q d q q d1b d1b rtb d0 d1 sel q d q q d2b rdrb lcb d0 d1 sel q d q q d3b rdtb do relay driver relay driver relay driver relay driver relay driver rddb relay driver rdda from ring voltage zero detect circuit from fault detect circuit internal internal from ring-trip circuit internal from loop closure circuit internal 8-bit shift resistor data latches to internal state control combinational logic circuitry indicates external package mode
L8575 advance data sheet dual-resistive, low-cost slic march 1997 24 lucent technologies inc. operating states each channel of the L8575 has four operating states: active, test, powerdown with relay driver rdd on, and powerdown with relay driver rdd off. these states are selected using 2 bits, d0 and d1, via the serial interface according to the truth table shown below. table 15. truth table for d1 and d0 logic input d2 operates the ringing relay driver, rdr, independent of the state of bits d0 and d1; however, the ring-trip detector is enabled only when d2 operates the ringing relay driver. hence, the ringing relay driver is not interchangeable with any of the other relay driv- ers. logic input d3 operates the test relay driver, rdt, independent of the state of bits d0 and d2. active state this is the normal operating state (talk state) of the channel. all circuits are operational. the tip drive cur- rent source sinks 5.6 madc from pt; the ring drive current source sinks 5.6 madc into pr. test state this is the test state of the channel. it is the same as the active state except that the ring drive current source is saturated to ground and the tip driver current source is saturated to v bat . this forces the loop-closure and ring-trip detectors to indicate an off-hook. this state is valid only when the ringing relay is not operated (d2 = 0). powerdown state with relay driver rdd operated this is the disconnect state of the channel. it is the same as the powerdown state except that relay driver rdd is also operated. when required, this relay may be used to disconnect the external dc feed resistors in order to provide a high-impedance termination to the subscriber loop. powerdown state this is the normal idle state (scan state) of the channel. the loop-closure, ring-trip, and common-mode fault detectors are active, but all other circuits are shut down to conserve power. all circuits common to both chan- nels remain active. the powerdown of channel a does not affect an active channel b and vice-versa. ringing state (d2 = 1) when d2 = 1, the ringing relay driver is activated. the operational state of the slic is unaffected except for the ring-trip and fault detectors. the digital portion of the ring-trip detector is enabled when d2 = 1 (relay drive ac- tivated) and disabled when d2 = 0 (relay drive deacti- vated). the ring-trip detector functions properly only when d2 = 1 so that a valid ringing signal (ac and dc) is present. when d2 = 0, the digital portion of the ring-trip detector is bypassed so that most of the ring-trip circuit can be tested in the test state. when d2 = 1, the fault detector is also disabled (flt forced to 0). d1 d0 state 1 1 channel active. 1 0 channel test. 0 1 channel powerdown and relay rdd driver on (rdd low). 0 0 channel powerdown. relay rdd driver off/rdd high.
lucent technologies inc. 25 advance data sheet L8575 march 1997 dual-resistive, low-cost slic supervision off-hook detection the off-hook detection threshold is a function of the dc feed resistors r 1 and r 2 , and of a ratio of resistors that are ?ed on the L8575 silicon die. thus, when r 1 = r 2 = 300 w , the off-hook threshold is set at 4 k w . this relationship is shown in the equation below: where, r t is the loop closure threshold r 1 = r 2 = dc feed resistors = 300 w where, r t1 and r t2 are internal resistors r t1 = 170 k w r t2 = 130 k w thus, ring-trip threshold 12-3424(f) figure 9. ring-trip threshold ring-trip threshold (figure 9) is calculated as follows: at ring-trip: if, v bat = v 20 hz (dc) then, r rth = r rf r rf = 1 m w ; r l (ring-trip) = 6 k w [avg: 2 k w & 10 k w ] ring-trip requirements n ringing signal: ?voltage: minimum 35 vrms, maximum 100 vrms. ?frequency: 17 hz to 23 hz. ?crest factor: 1.4 to 2. n ringing trip: ? 100 ms (typical), 250 ms (v bat = ?3 v, loop length = 530 w ). n pretrip: ?the circuits in figure 10 will not cause ringing trip. 12-2572 (c) figure 10. ring-trip circuits r t r 1 r 2 + 1 2 k w ------------ 1 ---------------------- = k r t1 r t1 r t2 + --------------------------- 0.4333 w == r t 300 w 300 w + 1 2 130 k w 130 k w 170 k w + --------------------------------------------- ? ?? ------------------------------------------------------ 1 --------------------------------------------------------------- - 3900 w ? 4 k w == loop resistance r l tip ring 300 w r rf r1 300 w r rf r rth c rf rtn rtp v rtn (dc) = v bat z v bat 2 ------------- - ? ?? r rf r rth -------------- - ? ?? 300 w r l 600 w + ------------------------------ - ? ?? v 20 hz (dc) = r rf 2r rth ------------------ 300 w r l 600 w + ----------------------------- - = 1 r l 600 w ------------------ - + ? ?? r rth = 11 m w \ 2r rf c rf 100 ms ? c rf = 0.047 m f \ ring ring ring 100 w 10 k w 6 ? tip tip tip 2 ? 200 w switch closes < 12 ms
L8575 advance data sheet dual-resistive, low-cost slic march 1997 26 lucent technologies inc. supervision (continued) fault detection the dc feed resistors r 1 and r 2 need to be designed to survive lightning surges and to dissipate power associ- ated with a ring ground dc fault and speci?d ac power cross faults?oth in a sneak under and full surge type fault. under certain sustained fault conditions, r 1 and r 2 could fail when they are required to survive. for this reason, a per-channel fault detector is included on the L8575. when the voltage across either r 1 and r 2 is a nominal 36 v (maximum 39 v), the fault detect bit, flt in the serial data output, will go high, as calculated below: flt = 1, if |v tip | > 36 v nominal or |v ring ?v bat | > 36 v nominal, which corresponds to dc power in r 1 or r 2 > 4 w the control logic on the line card detects flt is high and opens an external electromechanical relay to iso- late the resistors from the loop, enabling the resistors to survive extended power cross. (note the emr is the test in or test out emr, and this relay is driven by one of the internal relay drivers on the L8575 slic.) with an external 0.1 m f capacitor on pin cflt, a no- fault to fault delay of 10 ns to 30 ms is provided in the fault detector. this prevents transients on tip and ring from tripping the fault detector when a fault is not present. there is a release delay (fault to no-fault) of 1.6 t to 2.5 t, where t is the no-fault to fault delay time. zero voltage current cross the L8575 provides a bit, rza (and rzb for channel b), in the serial data stream which gives an indication when the ringing voltage is crossing zero. this signal bit may be used in timing the application and removal of the ringing signal. relay drivers six relay drivers, three relay drivers per channel, are included on the L8575 slic. the output of these driv- ers are package nodes rdd (a&b), rdr (a&b), and rdt (a&b). drivers rdr (a&b) are controlled by input bits d2 (a&b) on the serial input stream. drivers rdt(a&b) are controlled by input bits d3 (a&b) on the serial input stream. in these cases, a logic 1 on d2 or d3 activates the respective relay driver. relay drivers rdd (a&b) are controlled per the truth table (see table 2) via bits d0 (a&b) and d1 (a&b). in order to activate driver ddr, d0 = logic 1 and d1 = logic 0. note that with d0 = logic 1 and d1 = logic 0, the slic is set to the channel powerdown state. relay drivers rdr (a&b) must be used for the ring relay function because the ring-trip detector is enabled only when d2 is high; that is, when d2 operates the ringing relay driver (rdr). hence, the test and ringing relay drivers are not interchangeable. when relay driver rdd is active, the L8575 is forced into a powerdown state. thus, using rdd with the test- in relay is not appropriate. this relay may be used for test out or as a channel isolation relay. relay driver rdt is controlled by d3 in the serial bit stream. logic input d3 operates driver rdt indepen- dent of the state of bits d0, d1, and d2. rdt may be used with a test-in, test-out, or channel isolation relay.
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 27 dc characteristics i/v characteristics resistors r 1 and r 2 are the dc feed resistors. r1 is connected from battery to ring, and r2 is connected from tip to ground. the dc loop current is fed to the subscriber loop via these resistors. these resistors will set the dc i/v template for the line circuit, with the i/v template being linear with a ?/600 w slope. no con- stant current region at short dc loops is provided by resistors r 1 and r 2 or the L8575 slic. the dc tip/ring voltage under open loop conditions is 3.36 v less than battery. in order to drive an on-hook ac signal, the tip and ring voltage must be set to a value less than the battery voltage. the amount that the open loop voltage (v oc ) is decreased relative to the battery (v bat ) is referred to as the overhead voltage (v oh ). this overhead voltage is due to 5.6 ma of bias current ?w from both the tip and ring current drive ampli?rs ?w through resistors r2 and r1, respectively. thus, the overhead is given by: v oh = (r 1 x 5.6 ma) + (r 2 x 5.6 ma) v oh = (300 x 5.6 ma) + (300 x 5.6 ma) = 3.36 v the nominal dc i/v template for the L8575 slic is shown in figure 11. 12-3430(f).r1 figure 11. L8575 slic i/v template loop length the loop range equation is given by: where, r l is the dc resistance of the subscriber loop. i l is the dc loop current. |v bat | is the magnitude of the battery voltage. v oh is the overhead voltage?ominal 3.36 v. r 1 = r 2 = dc feed resistors = 300 w. thus, for a nominal ?8 v battery with a minimum 18 ma loop requirement, the loop range will be: r l = 1880 w 20 80 60 0 5 10 15 20 35 40 0 70 50 30 10 25 30 40 45 50 v t-r (v) i loop (ma) v oc (44.7) v bat (48) r l v bat v oh i l ---------------------------------- r 1 r 2 = r l 48 v 3.36 v 0.018 a -------------------------------------- - 300 w 300 w =
L8575 advance data sheet dual-resistive, low-cost slic march 1997 28 lucent technologies inc. ac design codec features and selection summary there are four key ac design parameters: n termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to mini- mize echo return to the telephone set. n transmit gain is measured from the 2-wire port to the pcm highway. n receive gain is done from the pcm highway to the transmit port. n hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. at this point in the design, the codec needs to be select- ed. the discrete network between the slic and the co- dec can then be designed. below is a brief codec feature and selection summary. first-generation codecs these perform the basic filtering, a/d (transmit), d/a (receive), and m -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid balance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog output stages, and m -law/a-law selectability. this generation of codec has the lowest cost. it is most suitable for applications with fixed gains, termination impedance, and hybrid balance. second-generation codecs this class of devices includes a microprocessor inter- face for software control of the gains and hybrid bal- ance. the hybrid balance is included in the device. ac programmability adds application flexibility and saves several passive components. it also adds several i/o latches that are needed in the application. it does not have the transmit op amp, since the transmit gain and hybrid balance are set internally. third-generation codecs this class of devices includes the gains, termination im- pedance, and hybrid balance?ll under microproces- sor control. depending on the device, it may or may not include latches. in the codec selection, increasing software control and ?xibility are traded for device cost. to help decide, it may be useful to consider the following: n will the application require only one value for each gain and impedance? n will the board be used in different countries with dif- ferent requirements? n will several versions of the board be built? if so, will one version of the board be most of the production volume? n does the application need only real termination impedance? n does the hybrid balance need to be adjusted in the ?ld?
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 29 ac design (continued) design equations the following section gives the relevant design equa- tions to choose component values for any desired gain, termination and balance network, assuming a complex termination is desired. complex termination will be speci?d in one of the two forms shown below: 12-3425(f) figure 12. equivalent complex terminations both forms are equivalent to each other, and it does not matter which form is speci?d. the component val- ues in the interface circuit of figure 12 are calculated assuming the parallel form is speci?d. if the termina- tion impedance to be synthesized is speci?d in the series form, convert it to the parallel form using the equations below: note that if the termination impedance is speci?d as pure resistive: de?e the gain constant, k, as follows: where, r x = desired receive (or pcm to tip/ring) gain in db t x = desired transmit (or tip/ring to pcm) gain in db |z t | 1 khz is the magnitude of the complex termina- tion impedance z t being synthesized, calculated at 1000 hz. this equation assumes that the tlp of the codec is 0 dbm referenced to 600 w . the following equation applies when referring to figure 13: where, w = 2 p| | = 1000 hz cr 1 r 2 is de?ed per figure 12 (series form), and r1 r2 c r2 r1 c (series form) (parallel form) r 1 r 1 r 2 + = r 2 r 1 2 r 2 r 1 + r 2 ------------------------------ - = c c 12 r 1 r 2 ------ - r 1 r 2 ------ - ? ?? 2 ++ ------------------------------------------ - = r 2 r 2 0 and c = c ~ == = k rcv k 0 10 rx/20 for receive gain = k tx 1 k 0 ------ 10 tx/20 for transmit gain = k 0 z t 1 khz 600 ------------------------- - = = power transfer ratio z t w 2 c 2 r 1 r 2 2 r 1 r 2 j w r 2 2 c ++ 1 w 2 r 2 2 c 2 + -------------------------------------------------------------------------------------- - = z t w 2 c 2 r 1 r 2 2 r 1 r 2 ++ 1 w 2 r 2 2 c 2 + ----------------------------------------------------------- ? ? ?? 2 w r 2 2 c 1 w 2 r 2 2 c 2 + ---------------------------------- - ? ? ?? 2 + =
L8575 advance data sheet dual-resistive, low-cost slic march 1997 30 lucent technologies inc. ac design (continued) design equations (continued) 12-3429.c (f) figure 13. initial ac interface for complex termination between L8575 slic and t7504 codec note: dc blocking capacitors (c b ) not shown, c t and c r separate v rn receive interface + r t2 r rv2 r hb1 r gx gsx vfxin vfro 1/4 t7504 codec z t/r + v t/r i t/r +2.4 v c r 1/2 L8575 r gx1 r rv1 c t r t1 z irp + ax v xmt l rp v rn xmt i rp pt pr v bat ts rs v bat r 1 r 2 c 1 resistor module 200 k w 200 k w 100 k w 300 w 300 w 100 k w 1.4 k w 1.4 k w
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 31 ac design (continued) design equations (continued) the tip/ring differential current is given by: the voltage at pin xmt is given by: the component values in the ac interface of figure 13 are calculated (for the transmit and receive gains de?ed by the respective gain constants k rx and k rcv , and for the termination impedance seen in figure 12) using the following equations: 600 w = 2 x 300 w feed resistors r gx = 2 x k tx (r gx1 + r t1 ) the 300 w feed resistors contribute 600 w to the termi- nation impedance. the termination impedance associ- ated with the circuit in figure 13 consists of this inherent 600 w feeding impedance in parallel with: n a negative impedance, where, x n a positive impedance, where, x the negative and positive impedance terms are used to adjust the termination impedance from the inherent 600 w to any complex termination. note in the case of a pure 600 w dc termination, the two 300 w feed resistors provide this termination, and components r t1 , r t2 , and c t are not used in the ac interface circuit. using the circuit of figure 13, the ratio of capacitors c t and c r will affect the (transmit and receive) gain ?t- ness, and to a lesser degree the return loss of the line circuit. thus, depending on the requirements, c t and c r may need to be tight tolerance capacitors. if this is the case, capacitors c t and c r may be com- bined into a single capacitor with a looser tolerance. this is illustrated in figure 14. i t/r 200 i rp v rn z irp ----------- ? ?? = v xmt v t/r 2 ------------- - = r rv1 100r 1 k rcv ------------------ - = r rv2 100r 2 k rcv ------------------ - = c r k rcv c 100 ------------------- - = r gx1 r gx1 r t1 + ----------------------------- - r rv1 100 ------------- 1 600 --------- - 1 r 1 -------- ? ?? = c t c 100 --------- -1 r gx1 r t1 ------------- 1 100r 1 r rv1 ------------------ - + ? ?? + = r t2 r 2 c c t -------------- - = 2 100 --------- - r gx1 r gx1 r t1 + ----------------------------- - r t2 1 j w c t ------------- + ? ?? r gx1 r t1 + r t1 ----------------------------- - ? ?? 12-3426a(f) figure 14. revised ac interface c t and c r combined into a single capacitor c s xmt rt2 c t irp c r v fro rrv2 xmt rt2 irp c s = c t + c r v fro rrv2 rrv1 rrv1
L8575 advance data sheet dual-resistive, low-cost slic march 1997 32 lucent technologies inc. ac design (continued) design equations (continued) to scale c s (higher), increase c t (and decrease r t2 ) by increasing the r gx1 / (r gx1 + r t1 ) ratio by rearrang- ing the circuit in figure 13 and by adding resistor r sc from xmt to irp as shown in the ?ure below: 12-3427a(f) figure 15. addition of resistor r sc from xmt to irp then, once the gains and complex termination are set, if the hybrid balance network is identical to the termination impedance, then the hybrid balance is set by a single resistor (shown in figure 15) and is computed as fol- lows: the L8575 slic is ground referenced. however, a +5 v only codec, such as t7504, is referenced to +2.5 v. the L8575 slic has suf?ient dynamic range to accommo- date an ac signal from the codec that is referenced to +2.5 v without clipping distortion. with a ?8 v battery, the dc voltage at node xmt will be a nominal ?2 v or ?4 v. this is the common-mode dc voltage. this will cause a dc current ?w from the codec to the slic. this current will not affect ac performance, but it will effectively waste power. to avoid this wasted power consumption, block- ing capacitors can be added. the blocking capacitors block the dc path from any low impedance node at the codec to slic node xmt. blocking capacitors are added to the application diagram in figure 16. after the blocking capacitor c b is added, the above component values may have to be adjusted slightly to optimize performance. the effects of the blocking capacitor are best evaluated and optimized by circuit simulation. contact your lucent technologies microelectronics group account representative for information on availability of a pspice * model. figure 16 shows a complete reference design using the L8575 slic and t8502/3 codec. this line circuit is designed to meet the requirements of the peoples republic of china. the basic ac design parameters are listed below: termination impedance: 200 w + 680 w || 0.1 m f hybrid balance network: 200 w + 680 w || 0.1 m f transmit gain: 0 db receive gain: ?.5 db or ?.0 db notice that the interface circuit between the L8575 and t8502/3 is designed for a receive gain of ?.5 db. the t8502 codec offers a pin selectable receive gain of 0 db or ?.5 db. thus, via logic control, a receive gain of either ?.5 db or 7.0 db is achieved. the t8502/3 codec is a dual +5 v only codec. when used with the dual L8575 slic, a complete low-cost, dual-line circuit is achieved. * pspice is a registered trademark of microsim corporation. r t1 r sc irp c t r t2 xmt vrn r gx1 c b r gx1 r gx1 r t1 + ----------------------------- - r rv1 r sc || () 100 ------------------------------------ - 1 600 --------- - 1 r 1 --------- ? ?? r rv1 r rv1 r sc + ------------------------------ + = r hb r gx k rcv k tx -------------------------------- = v tip v ring () 2 ---------------------------------------- -
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 33 application diagram the following diagram and table show the basic components required with the L8575 slic. speci? component values are given in cases where the value is ?ed. in cases where the value may change (i.e., components that determine the ac interface), the value is not listed but equations to determine these values are given later in this document. table 16. external components required * power is continuous rms power. ?r 1 /r 2 = 1, with a tolerance of 0.35% for 50 db longitudinal balance, 0.2% for 58 db longitudinal balance. fuses on f1 and f2 provide fail-safe operation if excessive overvoltage conditions exist on tip and ring. they will not operate if the total power dissipation of the entire resistor network is >5.0 w at 85 c. ?r 3 x r 6 )/(r 4 x r 5 ) = 1 with a tolerance of 0. 35% for 50 db longitudinal balance, 0.2% for 58 db longitudinal balance. ? 9 /r 1 = 100 with a tolerance of 0.5%. comp. function implementation value attribute* r 1 dc feed protection resistor module 300 w 1.0%, 2 w ? r 2 dc feed protection resistor module 300 w 1.0%, 2 w ? r 3 transmit gain resistor module 100 k w 1.0%, 25 mw r 4 transmit gain resistor module 100 k w 1.0%, 25 mw r 5 transmit gain resistor module 200 k w 1.0%, 25 mw r 6 transmit gain resistor module 200 k w 1.0%, 25 mw r 7 protection resistor module 1.4 k w 2.0%, 0.1 w r 8 protection resistor module 1.4 k w 2.0%, 0.1 w r 9 battery noise cancellation resistor module 15 k w 10 mw c vcc v cc filter external 0.1 m f 20%, 10 v c vdd v dd filter external 0.1 m f 20%, 10 v c bat v bat filter external 0.1 m f 20%, 100 v r cbn battery noise cancellation external 301 k w 1%, 1/16 w c cbn battery noise cancellation external 0.1 m f 20%, 100 v c rf ring trip external 0.1 m f 20%, 100 v r rf1 ring trip external 1 m w 20%, 100 v r rf2 ring trip external 1 m w 1%, 1/16 w r rth ring trip threshold external 11 m w 1%, 1/16 w c flta fault filter external 0.1 m f 20%, 100 v c b1 dc blocking external 0.1 m f 20%, 50 v c b2 dc blocking external 0.1 m f 20%, 50 v r t1 ac interface external 34 k w 1%, 1/32 w r t2 ac interface external 7.32 k w 1%, 1/32 w r gx ac interface external 150 k w 1%, 1/32 w r gx1 ac interface external 52.3 k w 1%, 1/32 w r rv1 ac interface external 113 k w 1%, 1/32 w r rv2 ac interface external 35.7 k w 1%, 1/32 w c2 or c s ac interface external 2.7 nf 5%, 10 v r hb1 ac interface external 221 k w 1%, 1/32 w
L8575 advance data sheet dual-resistive, low-cost slic march 1997 34 lucent technologies inc. application diagram (continued) 12-3308(f).a figure 16. typical application diagram with blocking capacitors (c b ) included 18 ptb 13 tsb 12 xmtb 14 rsb 44 clk 43 en 3 di 2 do 1.4 k w kta 37 38 30 7 +5 d rdta rdra rdda rddb pta tsa 300 w 200 k w 28 33 34 xmta 100 k w xmta kta2 tip test out bus (channel a) kta1 ring 100 k w 200 k w 1.4 k w 32 rsa 27 pra 36 rtpa kra2 1 m w 0.1 m f 35 rtna 1 m w 300 w 11 m w kra1 vrng (ringing v bat 19 prb 10 rtpb 11 rtnb 301 k w cbna 24 cbnb 22 0.1 m f 0.1 m f v bat v bat 21, 25 0.1 m f agnd 20, 26 v dda 23 +5 a same as channel a same as channel a 4 cfltb 15 rgbnb 16 vrnb 17 irpb c b2 r rv2 r t2 xmta termination/hybrid 200 w + 680 w ii 0.1 m f 2.7 nf 29 irpa 113 k w 0.1 m f xmta 221 k w 52.3 k w r gx 34 k w 30 vrna vfro(n) vfxin(n) gsx(n) 1/2 t8502/3 codec 15 k w 31 rgbna 0.1 m f 42 cflta serial interface buses to control logic 8 rdrb 9 rdtb 5, 41 v ddd 0.1 m f dg 6, 40 dgnd (office battery) thick film resistor r x = ?.5 db/?.0 db r rth r f2 r 2 r 8 r 6 r 4 r 3 r 5 r f1 thick film resistor c rf r 1 module supply) module r 7 L8575 r 9 kta kta ktb ktb ktb 35.7 k w 7.32 k w 0.1 m f 150 k w r t1 r rv1 c s = c t + c r r gx1 c b1 r hb2 c vdd c flta t x = 0 db gs gain c cbn c bat c vcc r cbn select
advance data sheet L8575 march 1997 dual-resistive, low-cost slic lucent technologies inc. 35 outline diagram 44-pin plcc dimensions are in millimeters. 5-2506r7 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
L8575 a d v ance data sheet dual-resistive , l o w-cost slic ma r ch 1997 for additional information, contact your microelectronics group account manager or the following: interne t : http://ww w .lucent.com/mic r o u . s .a. : microelectronics grou p , lucen t t echnologies inc., 555 union boul e v ard, room 30l-15p-ba, allent o wn, p a 18103 1-800-372-2447 , f ax 610-712-4106 (in cana d a : 1-800-553-2448 , f ax 610-712-4106), e-mail docmaster@mic r o.lucent.com asia p a cific: microelectronics grou p , lucen t t echnologies singapore pt e . ltd., 77 science p a r k d r i v e , #03-18 cintech iii, singapore 118256 t el . (65) 778 8833 , f ax (65) 777 7495 j a p an : microelectronics grou p , lucen t t echnologies j apan ltd., 7-18, higashi-gotanda 2-chom e , shinag a w a-ku , t ok y o 141, j apan t el . (81) 3 5421 1600 , f ax (81) 3 5421 1700 f or data requests in europe: mic r oelect r onics g r oup d a t aline : t el . (44) 1189 324 299 , f ax (44) 1189 328 148 f or technical inqui r ies in europe: central eu r ope : (49) 89 95086 0 (munich), no r thern eu r ope : (44) 1344 865 900 (bra c knell uk), france : (33) 1 41 45 77 00 (paris), southern eu r ope : (39) 2 6601 1800 (milan) or (34) 1 807 1700 (mad r id) lucen t t echnologies inc . rese r v es the r ight to ma k e changes to the product(s) or in f o r mation contained herein without notic e . no liability is assumed as a result of their use or application . no r ights under a n y patent accompa n y the sale of a n y such product(s) or in f o r mation. co p y r ight ?1997 lucen t t echnologies inc. all rights rese r v ed march 1997 ds97-140alc (replaces ds96-099lcas) printed on recycled paper o r dering in f ormation d e vice p a r t no. description p a c k age comcode lucL8575 bp dual-resisti v e slic 44-pin plcc 107890386 lucl857 5 bp-tr dual-resisti v e slic 44-pin plcc ( t ape & reel) 107890394

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